1. Field of the Invention
The present invention relates to a scrambler for a digital signal, and in particular to a self-synchronizing scrambler having a number of scrambler stages to which the digital signal bits are supplied in parallel.
2. Related Application and Patent
The subject matter of the present application is related to the subject matter of co-pending application Ser. No. 784,684 filed Sept. 25, 1985 of the same inventor and assignee, and to U.S. Pat. No. 4,663,501 issued May 5, 1987, also of the same inventor and assignee.
3. Description of the Prior Art
In digital signal transmission, pulse patterns may arise which include an unwanted dc component, or whose energy component is particularly high at certain discrete frequencies. In order to avoid such pulse patterns, the digital signal to be transmitted is scrambled with a pseudo-random sequence at the transmitter side by means of modulo-2 addition. Descrambling at the receiver side is undertaken by means of a further modulo-2 addition using the pseudo-random sequence employed at the transmitter side. Normally, synchronization of the pseudo-random generators employed at the transmitter side and the receiver side is necessary, however, it is known to avoid such synchronization by the use of so-called "free-wheeling", multiplicative, self-synchronizing scramblers and descramblers.
Upon further expansion of the digital telecommunications network, transmission devices for signals having an extremely high modulation rate are required between central points of the network. This requires scramblers and descramblers for digital signals having an extremely high clock frequency.
A scrambler for high clock frequency digital signals is described in Siemens Forschungs- und Entwicklungsberichte, Volume 6, No. 1 (1977) at pages 1 through 5. In this known device, the digital signals are scrambled in a plurality of parallel channels with correspondingly lower bit repetition rates, and the resulting signals are combined in multiplexers. The receiver side is analogously constructed, with the parallel descrambling taking place in a plurality of channels following a demultiplexer. In addition to a high circuit outlay, this known device requires synchronizing the multiplexer and demultiplexer with each other.
Scrambling for the individual hierarchy levels in the digital long-distance traffic network in Europe has been standardized by the postal authorities. For example, a scrambler with a scrambler period of 127 bits has been prescribed by the international postal authority in CCITT recommendations under V27 (revised).